Intel Core i7 with Nehalem’ architecture
The Core i7 is Intel’s first new CPU architecture since the original Core 2 shipped back in July, 2006. It’s hard to believe that the first Core 2 processors shipped over two years ago.
Since then, Intel has shipped incremental updates to the product line. Quad-core Core 2 CPUs arrived in November 2006, in the form of the QX6700. AMD was quick to point out that Intel’s quad-core solutions weren’t "true" quad-core processors, but consisted of two Core 2 Duo dies in a single package. Despite that purist objection, Intel’s quad-core solutions proved highly successful in the market.
The original Core 2 line was built on a 65nm manufacturing process. In late 2007, Intel began shipping 45nm CPUs, code-named Penryn. Intel’s 45nm processors offered a few incremental feature updates, but were basically continuations of the Core 2 line.
In the past year, details about Nehalem began dribbling out, culminating with full disclosure of the Core i7 architecture at the August, 2008 Intel Developer Forum. If you want more details about Nehalem’s architecture, that article is well worth a read. However, we’ll touch on a few highlights now.
* The Return of Hyper Threading
?Core i7 now implements Hyper-Threading, Intel’s version of simultaneous multithreading. Each processor core can handle two simultaneous execution threads. Intel added processor resources, including deeper buffers, to enable robust SMT support. Load buffers have been increased from 32 (Core 2) to 48 (Core i7), while the number of store buffers went from 20 to 32.
* New SSE4.2 instructions
?Intel enhanced SSE once again, by adding instructions that can help further speed up media transcoding and 3D graphics.
* Fast, unaligned cache access
?Before Nehalem, data needed to be aligned on cache line boundaries for maximum performance. That’s no longer true with Nehalem. This will help newer applications written for Nehalem, more than older ones, only because compilers and application authors often took great care to align data along cache line boundaries.
* Advanced Power Management
?The Core i7 actually contains another processor core, much tinier than the main cores. This is the power management unit, and is a dedicated microcontroller on the Nehalem die that’s not accessible from the outside world. Its sole purpose is to manage the power envelope of Nehalem. Sensors built into the main cores monitor thermals, power and current, optimizing power delivery as needed. Nehalem is also engineered to minimize idle power. For example, Core i7 implements a per core C6 sleep state.
* Turbo Mode
?One interesting aspect of Core i7’s power management is Turbo Mode (not to be confused with Turbo Cache). Turbo mode is a sort of automatic overclocking features, in which individual cores can be driven to higher clock frequencies as needed. Turbo Mode is treated as another sleep state by the power management unit, and operates transparently to the OS and the user.
The original Core 2 line was built on a 65nm manufacturing process. In late 2007, Intel began shipping 45nm CPUs, code-named Penryn. Intel’s 45nm processors offered a few incremental feature updates, but were basically continuations of the Core 2 line.
In the past year, details about Nehalem began dribbling out, culminating with full disclosure of the Core i7 architecture at the August, 2008 Intel Developer Forum. If you want more details about Nehalem’s architecture, that article is well worth a read. However, we’ll touch on a few highlights now.
* The Return of Hyper Threading
?Core i7 now implements Hyper-Threading, Intel’s version of simultaneous multithreading. Each processor core can handle two simultaneous execution threads. Intel added processor resources, including deeper buffers, to enable robust SMT support. Load buffers have been increased from 32 (Core 2) to 48 (Core i7), while the number of store buffers went from 20 to 32.
* New SSE4.2 instructions
?Intel enhanced SSE once again, by adding instructions that can help further speed up media transcoding and 3D graphics.
* Fast, unaligned cache access
?Before Nehalem, data needed to be aligned on cache line boundaries for maximum performance. That’s no longer true with Nehalem. This will help newer applications written for Nehalem, more than older ones, only because compilers and application authors often took great care to align data along cache line boundaries.
* Advanced Power Management
?The Core i7 actually contains another processor core, much tinier than the main cores. This is the power management unit, and is a dedicated microcontroller on the Nehalem die that’s not accessible from the outside world. Its sole purpose is to manage the power envelope of Nehalem. Sensors built into the main cores monitor thermals, power and current, optimizing power delivery as needed. Nehalem is also engineered to minimize idle power. For example, Core i7 implements a per core C6 sleep state.
* Turbo Mode
?One interesting aspect of Core i7’s power management is Turbo Mode (not to be confused with Turbo Cache). Turbo mode is a sort of automatic overclocking features, in which individual cores can be driven to higher clock frequencies as needed. Turbo Mode is treated as another sleep state by the power management unit, and operates transparently to the OS and the user.
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